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For full conference details: http://llvm.org/devmtg/2017-10/
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Wednesday, October 18 • 4:20pm - 5:05pm
Co-ordinating RISC-V development in LLVM

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RISC-V is a free and open instruction set architecture that has seen rapidly growing interest and adoption over the past couple of years. RISC-V Foundation members include AMD, Google, NVIDIA, NXP, Qualcomm, Samsung, and many more. Many RISC-V adopters, developers, and users are keen to see RISC-V support in their favourite compiler toolchain. This birds of a feather session aims to bring together all interested parties and better co-ordinate development effort - turning that interest in to high quality patches.

Issues to be discussed include:
* How best to co-ordinate development, minimising duplicated effort and bringing RISC-V to a top-tier architecture as quickly as possible
* How to test and support the huge number of possible RISC-V ISA variants (official extensions, as well as custom instructions).
* Support for variable-length vectors in the proposed RISC-V vector extension, and opportunities for LLVM developers to feed in to the ISA definition process
* Ways for companies who currently use a auto-generated RISC-V LLVM backend to move to building upon and contributing to the upstream codebase
* Opportunities for our development efforts to benefit the wider LLVM community, e.g. improvements to target-independent code, encouraging new contributors, and improving documentation

Speakers
avatar for Alex Bradbury

Alex Bradbury

Co-founder and Director, lowRISC CIC


Wednesday October 18, 2017 4:20pm - 5:05pm PDT
3 - BoF (Rm LL21CD)